Alif Semiconductor /AE512F80F55D5AS_CM55_HE_View /LPI2S /I2S_RFF0

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Interpret as I2S_RFF0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)RXCHFR

RXCHFR=Val_0x0

Description

Receive FIFO Flush Register 0

Fields

RXCHFR

Receive Channel FIFO Reset. Writing a 0x1 to this bit flushes the channel RX FIFO (this is a self clearing bit). The RX channel or block must be disabled prior to writing to this bit.

0 (Val_0x0): Does not flush the channel RX FIFO

1 (Val_0x1): Flushes the channel RX FIFO

Links

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